This invention is in the field of latch circuits or flip-flops and more specifically to a circuit capable of detecting a metastable condition of the latch circuit.
This application is related to my copending patent application entitled "Data Acquisition System Having a Metastable Sense Feature" Ser. No. 450,803.
Latch circuits typically pass data received at an input to an output in a transparent mode when a clock input is in a first logic state and retain data at the output in a hold mode when the clock input is in a second logic state. If the input data is asynchronous with the clock signal, the input data may be sampled during a transition from one logic state to another by the clock signal, thus resulting in invalid logic output levels. This condition is referred to as a metastable state or latch metastability.
To resolve the latch metastability problem, two prior art solutions have been used to prevent the undefined and invalid logic levels from propagating throughout the rest of the logic circuit and, eventually, to an external output pin. One prior art solution allows more time for the internal nodes and thus the output of the latch to eventually resolve into a valid logic level. This prior art solution is used in successive approximation ("SAR") type analog to digital ("A/D") converters. A second prior art solution "pipelines" the invalid logic level output of the initial latch through several latch circuits in order to eventually establish a valid logic level. This prior art solution is used in flash type A/D converters. The problem with both prior art solutions is that oftentimes circuit specifications neither permit extra time to be taken to resolve a metastable state nor permit the delay caused by pipelining of the invalid logic state.